suppose that the in the circuit above the propagation delay of the inverter is 1.5 ns and the propagation delay and settup times of the flip-flop are 3.5 ns and 2 ns respectively. what is the shortest clock period for the circuit that will not violate the time constraints

To design a steam turbine to produce 12,000 hp power. a engineer comsiders using a steady state stean low st 1160fr and engineer considers using a steady state steam flow at 1160°r and 450 psia to drive this steam turbine. the exhaust of the steam is cooled by the lake (vacuum). heat losing to the surroundings is measured at a rate of 555.55 btu/s. (a) sketch the system with the given conditions. (b) neglecting kinetic and potential energy changes from inlet to exit, determine the volumetric flow rate of the steam at the inlet, (ft'/hr). must clearly show unit conversions at crtical terms.