Create a VHDL code(design and testbench) that takes as input 8 numbers consisting of 6 bits binary digits and outputs their ranking (8 numbers consisting of 3 bits binary digits). The binary numbers are ranked
from the smallest to the largest and their ranking is outputted in binary.
Here is an example of inputs and outputs:
Inputs: 25, 1, 32, 27, 60, 12, 54, 48
Outputs: 2, 0, 4, 3, 7, 1, 6,5
The inputs and outputs are in binary.
Use the following entity declaration to describe your VHDL code:
library IEEE;
use IEEE. STD_LOGIC_1164. ALL;
use IEEE . NUMERIC_STD. ALL;
entity MSBN is
Port (In.1, In_2, In_3, In_4, In_5, In_6,In_7, In_8
(5 downto 0);
Out 1,0ut-2,0ut_3, Out-4,0ut_5,0ut_6,0ut_7,0ut_8
(2 downto 0));
end MSBN ;
std_logic_vector
out std_logic_vector
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