In this problem, you will design a transmission gate logic implementation of a simple sum-of-products Boolean expression and compare this implementation to a static CMOS logic circuit. Your manager assigns you the job of evaluating the suitability of a new semiconductor process for general-purpose digital circuit design and you decide to use the method of logical effort to do this evaluation quickly and without resorting to simulation. Suppose that in this process a minimum-sized NMOS transistor has W/L = 2/1 and a minimum-sized PMOS transistor with the same current drive has W/L = 5/1. You decide that a minimum-sized CMOS inverter should use minimum-sized transistors and based on source/drain junction capacitance calculations, it has a normalized parasitic delay (intrinsic delay) p_inv = 6/7. Consider the logic network shown in Figure 3. Using the method of logical effort, find the transistor sizes which minimize the delay along the path from A to F given that the first NAND2 gate uses minimum-sized PMOS transistors and has equal rise and fall times and that the normalized load (equivalent number of inverter input capacitances) at F is 57. What is the minimum (normalized) delay from A to F? Suppose the normalized parasitic delay for an inverter p_inv = 8/7. How much slower is the logic network than the solution you found for Problem 4.1 given the sizes you found above?