Cache block size (b) can affect both miss rate and miss latency. assuming a machine with a base cpi of 1, and an average of 1.35 references (both instruction and data) per instruction, find the block size that minimizes the total miss latency given the ollowing miss rates for various block sizes.

8: 4% 16: 3% 32: 2% 63: 1.5% 128: 1%
a.) what is the optimal block size for a miss latency of 20 × b cycles?

b.) what is the optimal block size for a miss latency of 24 + b cycles?

c.) for constant miss latency, wha
t is the optimal block size?