If we change load/store instructions to use a register (without an offset) as the address, these instructions no longer need to use the alu. (see exercise 4.15.) as a result, the mem and ex stages can be overlapped and the pipeline has only four stages.4.23.1 [10] < §4.5> how will the reduction in pipeline depth affect the cycle time? 4.23.2 [5] < §4.5> how might this change improve the performance of the pipeline? 4.23.3 [5] < §4.5> how might this change degrade the performance of the pipeline? 4.24 [10] < §4.7> which of the two pipeline diagrams below better describes the operation of the pipeline’s hazard detection unit? why? choice 1: ldur x1, [x2, #0]: if id ex me wb add x3, x1, x4: if id ex..me wb orr x5, x6, x7: if id..ex me wbchoice 2: ldur x1, [x2, #0]: if id ex me wb add x3, x1, x4: if id..ex me wb orr x5, x6, x7: if..id ex me wb