A dual processor SMP system includes an L1 data cache for each processor and employs the MESI protocol to maintain cache consistency. Each cache is a 2-way set associative copy-back cache that contains a total of 8192 cache lines each of which is 256 bytes in size. The Ways within each empty set are filled in the order Way0, Way1, Way2 then Way3. A write-allocate policy is used for each cache. One process, P1, runs on the first processor at the same time that another process, P2, runs on the other processor. P1 reads a variable X with an initial value of 80 that resides in memory at address 0x400804C0. After P1 reads X, P2 writes the value 156 into a variable Y located at memory address 0x400804F8. All caches are initially empty, so each cache line starts out in the invalid (I) state. a. After P1 first reads X, what is the MESI state of the line containing X in P1’s cache and how is P2’s cache affected? That is, what change (if any) occurs in the MESI state for the affected line or lines in the two caches?
b. After P2 writes Y, what is the MESI state of the line containing Y in P2’s cache and how is P1’s cache affected? That is, what change (if any) occurs in the MESI state for the affected line or lines?