Suppose that the components have the following propagation delay times.
Register: 2 ns
4-1 Multiplexer (or 8-1 Multiplexer): 1 ns
2-1 Multiplexer: 1 ns
ALU: 7 ns (Assume that all ALU operations, no matter how simple, take 6 ns)
Shifter: 4 ns
Zero detect: 1 ns
2-to-4 Decoder (or 3-to-8 Decoder): 2 ns
AND Gate: 1 ns
Branch Control: 2 ns
Instruction Decoder: 1 ns
Zero fill: 3 ns
Extend: 2 ns
PC : 2 ns
Memory access: 10 ns
Assume that the PC and the Registers use the same clock. Assume also that the PC and the
registers have the following set-up and hold times:
Set-up time: 2 ns
Hold time: 1 ns
In case final number is incorrect, write components to get partial credit.

Required:
a. What is the minimum clock cycle possible for an ADI instruction to always execute correctly?
b. What is the minimum clock cycle possible for a JMP instruction to always execute correctly?
c. What is the minimum clock cycle possible for a BRN instruction to always execute correctly?
d. What is the minimum clock cycle possible for an LD instruction to always execute correctly?
e. What is the minimum clock cycle possible for an SHR instruction to always execute correctly?

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What are the choices for this question?