HERES THE OTHER POEM
(quackity merch riddle)

The reset circuit used on the four 3-bit counters analyzed in this activity reset the counts to zero (000). it makes sense for the up-counters to start at zero (000), but the down-counters should start at seven (111). what would you need to change so that the 3-bit binary down counter with j/k flip-flops you just created would reset to seven (111)?

Write a computer program to calculate the three-phase fault current for a fault at f in figure 1.16, with the network normal, and with one line at a time removedproblems 1.1 write a computer program to calculate the three-phase fault current for a fault at f in figure 1.16, with the network normal, and with one line at a time removed 20 power system relaying from service. the positive-sequence impedance data are given in the accompanying table. use the commonly made assumption that all prefault resistance values are (1.0+j0.0) pu, and neglect all resistance values. calculate the contribution to the fault flowing through the cb b and the voltage at that bus. for each calculated case, consider the two possibilities: cb b2 closed or open. the latter is known as the stub-end fault í• figure 1.16 problem 1.1 system data for figure 1.16 from to positive sequence 0.0+j0.1 0.05j0.15 0.04 j0.2 0.01 jo.i 0.015 + j0.15 0.01 j0.19 0.01 +j0.19 0.03+j0.1 0.0+j0.08 6 6 6 from service. the positive-sequence impedance data are given in the accompanying table. use the commonly made assumption that all prefault resistance values are (1.0 + j 0.0) pu, and neglect all resistance values. calculate the contribution to the fault flowing through the cb b1, and the voltage at that bus. for each calculated case, consider the two possibilities: cb b2 closed or open. the latter is known as the “stub-end” fault.

Suppose we have a byte addressable computer that has a 32-byte cache with 8 bytes per block. the memory address is 8 bits long. the system accesses memory addresses (in hex) in this exact order: 6e, b9, 17, e0, 4e, 4f, 50, 91, a8, ab, ad, 93, and 94. (a) assuming the cache is direct mapped, what memory addresses will be in cache block 2 after the last address has been accessed? (b) assuming the cache is direct mapped, what is the hit ratio for the entire memory reference sequence given, assuming the cache is initially empty? (c) assuming the cache is 2-way set associative with a lru replacement policy, what is the hit ratio?