Normally, this would require 8 bits. However, this counter is a modulo 60 counter. So, it counts from 00 to 59 in BCD and then rolls over to 00. Since the most significant digit never exceeds 5, it only requires 3 bits. So, this counter requires a total of 7 bits. The entity declaration for modulo_60_counter is: entity modulo_60_counter is port( rst_n : in std_logic;-- active low synchronous reset clk : in std_logic;-- system clock clr_n : in std_logic;-- active low synchronous clear load_en : in std_logic;-- parallel load active high setting : in std_logic_vector(6 downto 0);-- load value cnt_en_1 : in std_logic;-- enable count 1 cnt_en_2 : in std_logic;-- enable count 2 max_count : out std_logic;-- maximum count flag count : out std_logic_vector(6 downto 0)-- BCD count ); end modulo_60_counter; Write the design description. Use the testbench provided to simulate the modulo_60_counter.