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What’s resistance in an electrical circuit ?

Acomputer has a two-level cache. suppose that 60% of the memory references hit on the first level cache, 35% hit on the second level, and 5% miss. the access times are 5 nsec, 15 nsec, and 60 nsec, respectively, where the times for the level 2 cache and memory start counting at the moment it is known that they are needed (e.g., a level 2 cache access does not even start until the level 1 cache miss occurs). what is the average access time?

How should you specify box sizes on a web page if you want the boxes to vary according to the font size of the text they contain? a. in pixels b. in inches c. as percentages d. in em units