Assume that a cache miss rate (both instruction and data) is 3%. If a processor has a CPI of 2 without any memory stalls and the miss penalty is 300 cycles for each miss. Also assume that 36% of instructions are loads and stores. (or the frequency of all loads and stores in a program is 36%.) a) Assume that I is the instruction count (# of instructions). Compute the total number of cycles for memory stalls. The total number of cycles for memory stalls x I

The idea that, for each pair of devices v and w, there’s a strict dichotomy between being “in range” or “out of range” is a simplified abstraction. more accurately, there’s a power decay function f (·) that specifies, for a pair of devices at distance δ, the signal strength f(δ) that they’ll be able to achieve on their wireless connection. (we’ll assume that f (δ) decreases with increasing δ.) we might want to build this into our notion of back-up sets as follows: among the k devices in the back-up set of v, there should be at least one that can be reached with very high signal strength, at least one other that can be reached with moderately high signal strength, and so forth. more concretely, we have values p1 ≥ p2 ≥ . . ≥ pk, so that if the back-up set for v consists of devices at distances d1≤d2≤≤dk,thenweshouldhavef(dj)≥pj foreachj. give an algorithm that determines whether it is possible to choose a back-up set for each device subject to this more detailed condition, still requiring that no device should appear in the back-up set of more than b other devices. again, the algorithm should output the back-up sets themselves, provided they can be found.\