A computer has a CPU that executes at 1GHz (1 billion cycles per second). The data sheet for a SPI (Serial Peripheral Interface) device controller says the maximum transfer speed is 100Mbps (100 million bits per second) and the maximum buffer size is 4096 bytes. A high-frequency 6-axis accelerometer/gyroscope sensor is connected by an external cable to the SPI controller and sends a 20 byte data packet every 10 μs. Every time a complete data packet is received by the controller it signals an interrupt to the CPU. A device driver has been written for the SPI controller, it has an ISR (interrupt service routine, aka interrupt handler) that can transfer a 20 byte data packet into main memory for later processing in about 100 CPU cycles. Required:
What percentage of CPU cycles will be used transferring data from the controller to main memory? Your answer should be in the form of a percentage (e. g. 20% of CPU cycles).