In 2020, an access time of 5 nsec would be typical for which element of the memory hierarchy in a desktop processor system? You must elaborate your response using the memory hierarchy terminology established within the lecture module content. For full credit, your response must consist of at least 5 complete sentences, but not have more than 10 sentences.

Suppose we have a byte addressable computer that has a 32-byte cache with 8 bytes per block. the memory address is 8 bits long. the system accesses memory addresses (in hex) in this exact order: 6e, b9, 17, e0, 4e, 4f, 50, 91, a8, ab, ad, 93, and 94. (a) assuming the cache is direct mapped, what memory addresses will be in cache block 2 after the last address has been accessed? (b) assuming the cache is direct mapped, what is the hit ratio for the entire memory reference sequence given, assuming the cache is initially empty? (c) assuming the cache is 2-way set associative with a lru replacement policy, what is the hit ratio?

This is not a factor that you should use to determine the content of your presentation. your audience your goals your purpose your technology

Asequential circuit contains a register of four flip-flops. initially a binary number n (0000 ≤ n ≤ 1100) is stored in the flip-flops. after a single clock pulse is applied to the circuit, the register should contain n + 0011. in other words, the function of the sequential circuit is to add 3 to the contents of a 4-bit register. design and implement this circuit using j-k flip-flops.