Write a report that captures your approach to a 6-bit synchronous 2-pipeline parallel adder. It should include: a. New pipeline architecture of your design where bit 0, bit 1, and bit 2 are in one pipeline stage; bit 3, bit 4, and bit 5 are in one pipeline stage. So, there are 2 pipeline stages.
b. VHDL code and testbench of the 6-bit synchronous 2-pipeline parallel adder. Note: Complete the VHDL testbench and determine the minimum clock period to continue obtaining correct pipeline adder results.
c. Your functional verification.

The following test cases for your synchronous pipeline adder are required:
A10 = (7,62)
B10 = (30, 63)
You must test for all A+B cases with initial carry-in Co = 0 and 1, which means you should verify a total of 4 1 2 = 8 input and output values.
Note: All answers in the waveforms must be labeled to show correct answers. Annotate the inputs and outputs in hexadecimal values next to their binary equivalents in the simulation waveform. Include all waveform snapshots.

Ihave a music player on my phone. i can buy songs, add them to playlists and play them. obviously it would be redundant to store each song in each playlist; each playlist is just a list of pointers to the songs. for this lab you will simulate this behavior. your program will need to have options to: add songs to the system library (you will store the text of the first line of the song, rather than the audio) add playlists add songs to a playlist list playlists play a playlist list all of the songs in the library with a count of how many times each song has been played remove a song from a playlist remove a playlist remove a song from the library (and thus from all playlists that contain it) note that we will not be checking many error cases. in real programming this would be bad, you should usually try to recognize and respond to as many types of errors as you can. in the context of class we are trying to acquaint you with as many concepts as possible, so for the sake of educational efficiency we will not be checking most errors in this lab, you may assume that your user provides correct input. you may add all appropriate error testing if you wish, but we will not be testing for it.