Suppose a byte-addressable computer using set-associative cache has 221 bytes of main memory and a cache of 64 blocks, where each cache block contains 4 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?

answer///64-bit architecture and gpt partitioning table;

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