Andre is planting sapling baby trees it takes him 30 minutes to plant three saplings and eat sapling takes the same amount of time to plant how long will it take Andre to plant 14 saplings?

Awould be a misconfiguration of a system that allows the hacker to gain unauthorized access, whereas is a combination of the likelihood that such a misconfiguration could happen, a hacker’s exploitation of it, and the impact if the event occurred.

Problems: 1. using textbooks, reference books, and internet as your source of research, draw the following microprocessor microarchitectures i. intel 8086 ii. motorola 68000 i atmel atmega32 iv. mips single cycle v. arm cortex-m3 write an hdl module for a hexadecimal seven-segment display decoder. the input is 4-bit binary representing a hex number (0-f), and the output is 8-bit seven segment display bits (a-h). thus, the decoder must handle the digits 10 - 15 to display a-f respectively, in addition to 0-9 numbers. 2. design a 4-bit left and right rotator (both outputs). first sketch schematic diagrams of your design. then implement your design using hdl coding. 3. 4. design a modified priority encoder that receives an 8-bit input, a7: 0 and produces a 3-bit output, y2o. y indicates the most significant bit of the input that is true. y should be 0 if none of the inputs are true. give a simplified boolean equation, sketch a schematic, and write an hdl code. 5.write an 8: 1 multiplexer module called mux8 with selection inputs s, data input d, and data output y. data input (d) and data output (v) are 32-bit wide

Acomputer has a two-level cache. suppose that 60% of the memory references hit on the first level cache, 35% hit on the second level, and 5% miss. the access times are 5 nsec, 15 nsec, and 60 nsec, respectively, where the times for the level 2 cache and memory start counting at the moment it is known that they are needed (e.g., a level 2 cache access does not even start until the level 1 cache miss occurs). what is the average access time?