Given these minterms (4,5,6,7,8,9,10,13,14,15), write a VHDL STATEMAENT for the function as a SOP Please use this entitiy declaration in formulating the statement Entitiy midterm is port (a, b,c, d : in STD_LOGIC: F: out STD_LOGIC); end midterm;

Match the following errors with their definitions. a. #name b. #value c. #ref d. 1. when a formula produces output that is too lengthy to fit in the spreadsheet cell 2. when you enter an invalid cell reference in a formula 3. when you type text in cells that accept numeric data 4. when you type in a cell reference that doesn’t exist