You are building a system around a single-issue in-order processor running at 2 ghz and the processor has a base cpi of 1 if all memory accesses are hits. the only instructions that read or write data from memory are loads (20% of all instructions) and stores (5% of all instructions). the memory system for this computer is composed of a split l1 cache that imposes no penalty on hits. both the i-cache and d-cache are direct mapped and hold 32kb each. you may assume the caches use write-allocate and write-back policies. the l1 i-cache has a 2% miss rate and the l1 d-cache has a 5% miss rate. also, 50% of all blocks replaced from l1 d-cache are dirty. the 512kb write-back, unified l2 cache has an access time of 12ns. of all memory references sent to the l2 cache in this system, 80% are satisfied without going to main memory. also 25% of all blocks replaced are dirty. the main memory has an access latency of 60ns. a. what is the overall cpi, including memory accesses?